/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

/** *****************************************************************************************************
 *  \file     Gpt_Register.h                                                                            *
 *  \brief    This file contains interface header for GPT MCAL driver                                   *
 *                                                                                                      *
 * <table>                                                                                              *
 * <tr><th>Date           <th>Version                                                                   *
 * <tr><td>2023/07/24     <td>1.0.0                                                                     *
 * </table>                                                                                             *
 *******************************************************************************************************/

#ifndef GPT_REGISTER_H
#define GPT_REGISTER_H

#ifdef __cplusplus
extern "C" {
#endif

/********************************************************************************************************
 *                                 Private Macro definition                                             *
 *******************************************************************************************************/
/**  max GPT module */
#define GPT_IP_MAX_MODULE  (12U)

/********************************************************************************************************
 *                                 Private Macro definition                                             *
 *******************************************************************************************************/

/* G0 and G1 common control */
#define GPT_COM_CTRL_ADDR32(tm) (BTM_BASE_ADDR32[tm])

/* G0 Timer enable */
#define GPT_CNT_G0_EN_ADDR32(tm) (BTM_BASE_ADDR32[tm] + (uint32)0x4U)
/* G0 Timer config */
#define GPT_CNT_G0_CFG_ADDR32(tm) (BTM_BASE_ADDR32[tm] + (uint32)0x8U)
/* G0 Timer config mask */
#define GPT_CNT_G0_CFG_MASK 0xffff007fUL
/* G0 Timer over flow */
#define GPT_CNT_G0_OVF_ADDR32(tm) (BTM_BASE_ADDR32[tm] + (uint32)0xCU)
/* G0 Timer value */
#define GPT_CNT_G0_VAL_ADDR32(tm) (BTM_BASE_ADDR32[tm] + (uint32)0x14U)
/* G0 Timer Hold value */
#define GPT_CNT_G0_HOLD_VAL_ADDR32(tm) (BTM_BASE_ADDR32[tm] + (uint32)0x18U)

/* G1 Timer config */
#define GPT_CNT_G1_CFG_ADDR32(tm) (BTM_BASE_ADDR32[tm] + (uint32)0x28U)
/* G1 Timer config mask */
#define GPT_CNT_G1_CFG_MASK 0xffff007fUL
/* G1 Timer status update regist */
#define GPT_CNT_G1_UPD_ADDR32(tm) (BTM_BASE_ADDR32[tm] + (uint32)0x38U)
/* G1 Timer status update regist mask */
#define GPT_CNT_G1_UPD_MASK 0x0fUL
/* G1 Timer Hold value */
#define GPT_CNT_G1_HOLD_VAL_ADDR32(tm) (BTM_BASE_ADDR32[tm] + (uint32)0x3CU)

/* INT status */
#define GPT_INT_STA_ADDR32(tm)    (BTM_BASE_ADDR32[tm] + (uint32)0x40U)
/* INT status enable */
#define GPT_INT_STA_EN_ADDR32(tm)    (BTM_BASE_ADDR32[tm] + (uint32)0x44U)
/* INT status enable mask */
#define GPT_INT_STA_EN_MASK 0x0fUL
/* INT signer enable */
#define GPT_INT_SIG_EN_ADDR32(tm)    (BTM_BASE_ADDR32[tm] + ((uint32)0x48U))
/* INT interrupt enable mask */
#define GPT_INT_SIG_EN_MASK 0x0fUL

/* G0 interrupt status bit */
#define GPT_IP_HW_CHANNEL_G0_IRQ    0x5U
/* G1 interrupt status bit */
#define GPT_IP_HW_CHANNEL_G1_IRQ    0xAU

/* Gpt us to s */
#define GPT_TIME_US (1000000UL)

/* Gpt G1 update flag signal mask */
#define GPT_CNT_G1_UPD_FLAG_SI_MASK (0x01UL << 2U)
/* Gpt G1 update over flow flag mask */
#define GPT_CNT_G1_UPD_FLAG_OVF_MASK (0x01UL << 0U)

/* counter interval statrt bit */
#define GPT_CNT_SI_VAL_MASK_START (24U)
/* counter interval bit wide */
#define GPT_CNT_SI_VAL_MASK_WIDTH (8U)
#define GPT_CNT_INC_VAL (0x01UL << 16U)

/* over flow status enable regist */
#define GPT_IP_OVFINT_EN_MASK_START(ch) ((2U + (uint32)(ch)))

/* G1 regist offset */
#define GPT_IP_REG_OFFSET_20H (0x20U)

#ifdef __cplusplus
}
#endif

#endif /* GPT_REGISTER_H */

/* End of file */
